36行Verilog写了个电脑:-)

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module cpu(input[31:0] clk, input[55:0] rom);
reg[7:0]    inst;    // instruction
reg[1:0]    op;      // op code
reg         ri;      // register index
reg[4:0]    immd;    // immediate number
reg[4:0]    rf[2];   // register file
wire        s;       // add caused <0?
reg[4:0]    pc;      // program counter
always @(clk) begin
    $monitor("%b %b %b %b", inst, rf[0], rf[1], s);
    pc = clk ? pc : 0;
    inst = rom >> (48 - pc * 8);
    op = inst[7:6]; ri = inst[5]; immd = inst[4:0];
    if (op == 'b00) begin rf[ri] = immd; pc++; end
    else if (op == 'b01) begin rf[ri] += immd; pc++; end
    else if (op == 'b10) pc += s ? immd : 1;
    else if (op == 'b11) begin
        if (!immd) $finish();
        pc += immd;
    end
end
assign s = (rf[0][4] | rf[1][4]);
endmodule
// How to pass array structure between two verilog modules?
// https://stackoverflow.com/questions/16369698/how-to-pass-array-structure-between-two-verilog-modules
// This is not possible in Verilog. (See sec. 12.3.3, Syntax 12-4 of the Verilog 2005 standard document, IEEE Std. 1364-2005.)
module suanpan;
reg[55:0]  rom[1];
integer    clk;
initial begin
$readmemb("rom.txt", rom);
$display("rom.txt: %b", rom[0]);
for(clk = 0; clk < 100; clk++) #1;
end
cpu cpu(clk, rom[0]);
endmodule

俺会写触发器: https://www.cnblogs.com/funwithwords/p/15728493.html

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